DMA
Contents
EDMA
EDMA(enhanced direct memory access)
TPCC & TPCC
EDMA 有两个很重要的controller：
– EDMA third-party channel controller (TPCC)
– EDMA third-party transfer controller (TPTC)
UDMA & NAVSS
NAVSS
NAVSS 是一个容器，它将在 SoC 中提供 DMA 服务所涉及的组件组合在一起。除此之外，其它的DMA comments 如DRUs, UTC, PDMAs. 存在NAVSS。
UDMA
UDMA is packet-oriented DMA.
UDMA 模块支持各种数据包类型的发送和接收。 UDMA 的架构旨在促进 SoC DMA 数据结构兼容数据包的分段和重新组装，这些数据包与每个连接外设的特定要求本机兼容的较小数据块。 DMA 内提供了多个 Tx 和 Rx 通道，允许多个
分段或重组操作正在进行中。 DMA 控制器维护每个通道的状态信息，这允许数据包分段和重组操作在通道之间进行时分复用，以便共享底层 DMA 硬件。
UTC (United Transfer Controller)
UTC 旨在执行与 EDMA 传输类似的功能以前的设备上使用的控制器引擎。 UTC引擎通常被归类为第三方DMA。 这个名称来自这样一个事实，即引擎实际上不是来源或正在移动的数据的接收器，而是执行该操作的中介第3方数据代表源和接收器移动。
UTC引擎通过PSI-L接口接受来自UDMA的传输响应消息，该接口提供在源读取接口和目标写入接口之间复制数据的指令。可以的操作序列包括多达4维的嵌套循环。指定了多种类型的传输请求消息，系统中的每个UTC实例可以支持所有类型或任何指定的子集。 当一个转移请求完成后，UTC将传输响应消息返回给始发UDMA。
UTC能够在处理传输请求时在指定的完成点生成事件。这些事件被发送回中断IR block。
DRU (Data Routing Unit)
DRU 是一个 UTC，它支持只有传输请求消息格式的块复制模式子集。 DRU通常将提供任何 DMA 引擎中最高性能的块复制数据移动能力在SoC内。
PDMA
外设 DMA 是一种简单的 DMA，其架构专门用于满足数据使用内存映射寄存器执行数据传输外设的传输需求。 PDMA 只负责用于执行与外围设备本身交互的数据移动事务。从给定外设读取的数据由 PDMA 源通道打包到 PSI-L然后发送到远程对等 UDMA-P 目标通道的数据流，然后
执行数据到内存的移动。同样，远程 UDMA-P 源通道从内存中获取数据并通过 PSI-L 将其传输到对等 PDMA 目标通道，然后执行对外围设备的写入。
外设 DMA 架构是异构 (UDMA + PDMA) 的。
外设通常基于 FIFO，不需要多维传输，因此 PDMA 传输引擎保持简单，只有几个维度（通常用于样本大小和 FIFO 深度）。
PDMA 中提供了多个源和目标通道，允许多个正在进行的同步传输操作。 DMA 控制器对于每个通道维护状态信息，并在通道之间采用循环调度，以便共享底层 DMA 硬件。
UDMA Block Diagram
AM6x Main NavSS: SW view and McASP UDMA sequence
A brief description of the sequence of the configuration steps is given below
- Setup “Proxy” to submit descriptors (this is an optional step)
- Setup a RX free ring and RX completion within ring accelerator. A ring acts as HW FIFO to accept DMA transfer descriptors from the SW and pass on to the UDMA
- Setup UDMA RX channel within UDMA
- Pair the UDMA RX channel thread ID with McASP PDMA thread ID in the PSI-L (Packet Streaming Interface – Link) network
- Setup static TR in PDMA channel for McASP
- Setup McASP to receive data
- Setup interrupt aggregator to receive RX packet completion event and convert to an interrupt 8. Setup interrupt router to route the interrupt to required CPU
A brief description of the sequence of steps as data flows through the SoC is given below
1. SW submits a DMA transfer descriptor to the RX free ring directly or via the “Proxy” HW
2. The descriptor is enqueue into the ring8 Migrating Applications from EDMA to UDMA using TI-RTOS
3. The descriptor is forwarded to the UDMA channel so that when data is received from McASP the data is stored at the buffer pointed to by the descriptor
4. As McASP receives data the data is sent over the PSI-L network to the “paired” UDMA channel.
5. UDMA RX channel receives the data
6. The received data is written to the buffer pointed by the previously enqueued descriptor
7. Once the complete data packet is received an event is generated over the ETL (Event Transport Lane) bus
1. The completed descriptor is written out to the RX completion queue (NOT shown in the figure)
8. The event is routed to a programmed interrupt within the interrupt aggregator
9. The interrupt aggregator route the event to the interrupt router
10. The interrupt router routes the event to the required CPU interrupt line
the figure below as example of DRU DMA transfer using UDMA
Main difference is here the descriptor is forwarded by the UDMA to the DRU (UTC) peripheral (step 4, 5).
Here the PSI-L network is used to transfer the descriptor.
The DRU then does the DMA transfer without the intervention of the UDMA (step 6).
The PSI-L network is not used for data transfer. When the DMA transfer completes the completion event is routed to the user via the ETL (step 7, 8, 9, 10)
Comparison of EDMA and UDMA features
参考
- EMDA : https://www.ti.com/lit/ug/spru234c/spru234c.pdf?ts=1626171272677&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US%2526searchTerm%253Dmigrating%2BApplication%2Bform%2BEDMA%2526nr%253D231
- EDMA3 FAQ
- Migrating_Applications_from_EDMA_to_UDMA_using_TI-RTOS.pdf
